The invention relates generally to a flash memory device. More particularly, it relates to a flash memory device capable of reading out other sectors during the program/erase operation.
Generally, during the program operation, if a voltage of about 5 volt is applied to the drain and a voltage of about 9 volt is applied to the control gate, electrons moving from the source to the drain are generating hot electrons in the drain at the boundary of the P-well. Then, the hot electrons are attracted to the floating gate by the bias of the control gate to thus increase the threshold voltage of the transistor that is formed by the floating gate, thus causing the cell to be a program state. In the program operation of the stack gate flash EEPROM, the efficiency in which the hot electrons are generated is an important factor.
Upon erase operation, if a voltage of about 5 volt is applied to the source and a voltage of about xe2x88x9210 volt is applied to the control gate (the drain is at a floating state), a so called F-N tunneling effect is generated through the tunnel oxide film due to the voltage potential between the floating gate and the source, so that the electrons exit toward the source. Thus, the threshold voltage of the transistor, formed by the floating gate, is reduced, thus causing the cell to be an erase state. Also, another erase method is to float the source and the drain, to apply a voltage of about xe2x88x928 volt to the control gate and to apply a voltage of about 8 volt to the P-well so that electrons in the floating gate can exit toward the P-well. In the erase operation of the stack gate flash EEPROM, the voltage potential between the floating gate and the source or the P-well becomes an important factor. Thus, the erase characteristic (rate) is determined by the ratio of the capacitance of the insulating film surrounding the floating gate to the capacitance of the dielectric film between the control gate and the floating gate. Therefore, the erase rate of the cell could not be made uniform unless the value of the capacitance is constant regardless of the number of the cells.
In the read-out operation, it recognizes data by applying a voltage of about 5 volt to the control gate and a voltage of about 1 volt to the drain and sensing the current flowing through the cell so that the on/off of the cell can be read.
During the operation, the conventional flash memory could read out the data on other flash memory cell after the program/erase operation is completed or suspended. However, as the program/erase operation of the flash memory takes a very long time compared to the read-out operation, the read-out operation, after the program/erase operation is finished, will hamper the entire operation of the system.
It is therefore an object of the present invention to provide a flash memory device capable of reading out other sectors during the program/erase operation.
In order to accomplish the above object, the flash memory device according to the present invention is characterized in that it comprises a bank register for selecting the program/erase state of each of the banks, a mode controller for outputting the mode signal of the bank selected by the bank register, an address controller for independently separating an external address into an internal address depending on the output from the bank register, and a plurality of banks for simultaneously performing the program/erase operation and the read-out operation, depending on the mode signal and the internal address.